// Tag SRAM, Data SRAM, LRU bits reg [19:0] tag [0:WAYS-1][0:LINE_SIZE-1]; reg [255:0] data [0:WAYS-1][0:LINE_SIZE-1];
always @(posedge clk_dst or negedge rst_n) begin if (!rst_n) sync, meta <= 2'b00; else sync, meta <= meta, sig_src; end
// ALU inside execute wire [31:0] alu_out = (opcode == ADD) ? ID_EX_rs1 + ID_EX_rs2 : ...;
// Tag SRAM, Data SRAM, LRU bits reg [19:0] tag [0:WAYS-1][0:LINE_SIZE-1]; reg [255:0] data [0:WAYS-1][0:LINE_SIZE-1];
always @(posedge clk_dst or negedge rst_n) begin if (!rst_n) sync, meta <= 2'b00; else sync, meta <= meta, sig_src; end Advanced Chip Design- Practical Examples In Verilog
// ALU inside execute wire [31:0] alu_out = (opcode == ADD) ? ID_EX_rs1 + ID_EX_rs2 : ...; // Tag SRAM, Data SRAM, LRU bits reg